PD488588FF Datasheet, PDF (49/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
Once the RDRAM is in ATTN, ATTNW, or ATTNR states, it will remain there until it is explicitly returned to the STBY
state with a RLX command. A RLX command may be given in an ROWR, COLC, or COLX packet (see the left side
of Figure 23-2). It is usually given after all banks of the RDRAM have been precharged; if other banks are still
activated, then the RLX command would probably not be given.
If a broadcast ROWA packet or ROWR packet (with the ATTN command) is received, the RDRAM’s power state
doesn’t change. If a broadcast ROWR packet with RLXR command is received, the RDRAM goes to STBY.
Figure 23-2 STBY Entry (left) and STBY Exit (right)
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
Power
State
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₀₃ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄ T₁₅ T₁₆
CTM/CFM
RLXR
RLXC
RLXX
t_AS
ATTN
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
STBY
Power
State
ROP a0
COCPOaP1 ^a1
COP a1
COP a1 COP a0
XOP a1 XOP a0
TFRM•tCYCLE
t_SA
STBY
ATTN
ROP=non-broadcast
ROWA or ROWR/ATTN
a0={d0, b0, r0}
a1={d1, b1, c1}
No COL packets may be
placed in the three
indicated positions; i.e. at
(TFRM-{1,2,3})•tCYCLE.
A COL packet to device d0
(or any other device) is okay at
(TFRM)•tCYCLE
or later.
A COL packet to another device
(d1!=d0) is okay at
(TFRM-4)•tCYCLE
or earlier.
Figure 23-3 shows the NAP entry sequence (left). NAP state is entered by sending a NAPR command in a ROW
packet. A time tASN is required to enter NAP state (this specification is provided for power calculation purposes). The
clock on CTM/CFM must remain stable for a time tCD after the NAPR command.
Figure 23-3 NAP Entry (left) and PDN Entry (right)
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₀₃ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
Power
State
ROP a0
(NAPR)
t_CD
restricted ROP a1
t_NPQ
COP a0 restricted COP a1
XOP a0
XOP a1
CTM/CFM
ROW2
..ROW0
COL4
..COL0
t_ASN
ATTN/STBY ^Note
DQA8..0
DQB8..0
NAP
Power
State
ROP a0
(PDNR)
COP a0
XOP a0
t_CD
restricted ROP a1
t_NPQ
restricted COP a1
XOP a1
a0={d0, b0, r0, c0}
a1={d1, b1, c1, c1}
No ROW or COL packets directed
to device d0 may overlap the
restricted interval. No broadcast
ROW packets may overlap
the quiet interval.
ROW or COL packets to a device
other than d0 may overlap the
restricted interval.
t_ASP
ATTN/STBY ^Note
PDN
ROW or COL packets directed
to device d0 after the restricted
interval will be ignored.
Note The(eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry
The RDRAM may be in ATTN or STBY state when the NAPR command is issued. When NAP state is exited, the
RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is
specified with NAPR, then the RDRAM will return to STBY state when NAP is exited.
Figure 23-3 also shows the PDN entry sequence (right). PDN state is entered by sending a PDNR command in a
ROW packet. A time tASP is required to enter PDN state (this specification is provided for power calculation
purposes). The clock on CTM/CFM must remain stable for a time tCD after the PDNR command.
Data Sheet E0251N20 (Ver. 2.0)
49