PD488588FF Datasheet, PDF (57/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
Notes 1. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is
effectively 0.0 to 0.0.
2. With VIL,CMOS = 0.5 VCMOS − 0.6 V and VIH,CMOS = 0.5 VCMOS + 0.6 V
3. Effective hold becomes tH4’=tH4 + [PDNXA • 64 • tSCYCLE + tPDNXB,MAX ] − [PDNX • 256 • tSCYCLE ]
if [PDNX • 256 • tSCYCLE ] < [PDNXA • 64 • tSCYCLE + tPDNXB,MAX ]. See Figure 23-4.
Data Sheet E0251N20 (Ver. 2.0)
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