PD488588FF Datasheet, PDF (56/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
27. Timing Conditions
Timing Conditions
Symbol
Parameter
MIN.
tCYCLE
CTM and CFM cycle times
-C80
2.50
tCR, tCF
CTM and CFM input rise and fall times
0.2
tCH, tCL
CTM and CFM high and low times
40%
tTR
CTM-CFM differential
(MSE/MS=0/0)
0.0
(MSE/MS=1/1) ^Note1
0.9
tDCW
Domain crossing window
–0.1
tDR, tDF
DQA/DQB/ROW/COL input rise/fall times
0.2
tS, tH
DQA/DQB/ROW/COL-to-CFM
setup/hold time
tCYCLE=2.50ns
0.200
tDR1, tDF1
SIO0, SIO1 input rise and fall times
—
tDR2, tDF2
CMD,SCK input rise and fall times
—
tCYCLE1
SCK cycle time - Serial control register transactions
1,000
SCK cycle time - Power transitions
10
tCH1, tCL1
tS1
tH1
SCK high and low times
CMD setup time to SCK rising or falling edge ^Note2
CMD hold time to SCK rising or falling edge ^Note2
4.25
1.25
1
tS2
SIO0 setup time to SCK falling edge
40
tH2
SIO0 hold time to SCK falling edge
40
tS3
PDEV setup time on DQA5..0 to SCK rising edge
0
tH3
PDEV hold time on DQA5..0 to SCK rising edge
5.5
tS4
ROW2..0, COL4..0 setup time for quiet window ^Note3
–1
tH4
ROW2..0, COL4..0 hold time for quiet window
5
VIL, CMOS
VIH, CMOS
tNPQ
CMOS input low voltage - over / undershoot voltage
duration is less than or equal to 5 ns
CMOS input high voltage - over / undershoot voltage
duration is less than or equal to 5ns
Quiet on ROW / COL bits during NAP / PDN entry
–0.7
VCMOS/2 + 0.6
4
tREADTOCC Offset between read data and CC packets (same device)
12
tCCSAMTOREAD Offset between CC packet and read data (same device)
8
tCE
CTM/CFM stable before NAP/PDN exit
2
tCD
CTM/CFM stable after NAP/PDN entry
100
tFRM
ROW packet to COL packet ATTN framing delay
7
tNLIMIT
Maximum time in NAP mode
—
tREF
Refresh interval
—
tCCTRL
Current control interval
34 tCYCLE
tTEMP
Temperature control interval
—
tTCEN
TCE command to TCAL command
150
tTCAL
TCAL command to quiet window
2
tTCQUIET
Quiet window (no read data)
140
tPAUSE
RDRAM delay (no RSL operations allowed)
—
tBURST
Interval after PDN or NAP (with self-refresh) exit in which
—
all banks of the RDRAM must be refreshed at least once.
MAX.
3.83
0.5
60%
1.0
1.0
+0.1
0.65
—
Unit
ns
ns
tCYCLE
tCYCLE
tCYCLE
ns
ns
Figures
Figure 30-1
Figure 30-1
Figure 30-1
Figure 22-1
Figure 30-1
Figure 35-1
Figure 31-1
Figure 31-1
5.0
2.0
—
—
—
—
—
—
—
—
—
—
—
+(VCMOS/2–0.6)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCYCLE
tCYCLE
V
Figure 33-1
Figure 33-1
Figure 33-1
Figure 33-1
Figure 33-1
Figure 33-1
Figure 33-1
Figure 33-1
Figure 33-1
Figure 23-4, 33-2
Figure 23-4, 33-2
Figure 23-4
Figure 23-4
VCMOS + 0.7
V
—
—
—
—
—
—
10
32
100 ms
100
—
2
—
200
200
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
µs
ms
—
ms
tCYCLE
tCYCLE
tCYCLE
µs
µs
Figure 23-3
Figure 25-1
Figure 25-1
Figure 23-4
Figure 23-3
Figure 23-2
Figure 23-1
Figure 24-1
Figure 25-1
Figure 25-2
Figure 25-2
Figure 25-2
Figure 25-2
Figure 22-1
Figure 24-2
56
Data Sheet E0251N20 (Ver. 2.0)