PD488588FF Datasheet, PDF (33/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
20. Control Register Packets
Table 20-1 summarizes the formats of the four packet
types for control register transactions. Table 20-2
summarizes the fields that are used within the packets.
Figure 20-1 shows the transaction format for the SETR,
CLRR, and SETF commands. These transactions consist
of a single SRQ packet, rather than four packets like the
SWR and SRD commands. The same framing sequence
on the CMD input is used, however. These commands are
used during initialization prior to any control register read
or write transactions.
Figure 20-1 SETR, CLRR, SETF Transaction
T₄
SCK
T₂₀
1
0
1
CMD _{1111 0000}
00000000...00000000
0
1
SIO0
SRQ packet - SETR/CLRR/SETF
0
The packet is repeated
from SIO0 to SIO1
1
SIO1
SRQ packet - SETR/CLRR/SETF
0
SCK
Cycle
0
1
2
3
4
5
6
7
SIO0 or
SIO1
for SRQ
rsrv
rsrv
rsrv
rsrv
rsrv
SDEV5
SOP3
SOP2
SIO0 or
SIO1
for SA
rsrv
rsrv
rsrv
rsrv
SA11
SA10
SA9
SA8
Table 20-1 Control Register Packet Formats
SIO0 or
SIO1
for SINT
0
0
0
0
0
0
0
0
SIO0 or
SIO1
for SD
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SCK
Cycle
8
9
10
11
12
13
14
15
SIO0 or
SIO1
for SRQ
SOP1
SOP0
SBC
SDEV4
SDEV3
SDEV2
SDEV1
SDEV0
SIO0 or
SIO1
for SA
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SIO0 or
SIO1
for SINT
0
0
0
0
0
0
0
0
SIO0 or
SIO1
for SD
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Field
rsrv
SOP3..SOP0
Table 20-2 Field Description for Control Register Packets
Description
Reserved. Should be driven as “0” by controller.
0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0010 - SETR. Set Reset bit, all control registers assume their reset values. ^Note 16 tSCYCLE delay until CLRR
command.
0100 - SETF. Set fast (normal) clock mode. 4 tSCYCLE delay until next command.
1011 - CLRR. Clear Reset bit, all control registers retain their reset values. ^Note 4 tSCYCLE delay until next
command.
1111 - NOP. No serial operation.
SDEV5..SDEV0
SBC
SA11..SA0
SD15..SD0
0011, 0101 – 1010, 1100 – 1110 – RSRV. Reserved encodings.
Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM to
which the transaction is directed.
Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection.
Serial address. Selects which control register of the selected RDRAM is read or written.
Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.
Note The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be
used in isolation. This is called “SETR/CLRR Reset”.
Data Sheet E0251N20 (Ver. 2.0)
33