PD488588FF Datasheet, PDF (52/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
24. Refresh
RDRAMs, like any other DRAM technology, use volatile storage cells which must be periodically refreshed. This is
accomplished with the REFA command. Figure 24-1 shows an example of this.
The REFA command in the transaction is typically a broadcast command (DR4T and DR4F are both set in the
ROWR packet), so that in all devices bank number Ba is activated with row number REFR, where REFR is a control
register in the RDRAM. When the command is broadcast and ATTN is set, the power state of the RDRAMs (ATTN or
STBY) will remain unchanged. The controller increments the bank address Ba for the next REFA command. When
Ba is equal to its maximum value, the RDRAM automatically increments REFR for the next REFA command.
On average, these REFA commands are sent once every tREF / 2 ^BBIT+RBIT (where BBIT are the number of bank address
bits and RBIT are the number of row address bits) so that each row of each bank is refreshed once every tREF
interval.
The REFA command is equivalent to an ACT command, in terms of the way that it interacts with other packets (see
Table 6-1). In the example, an ACT command is sent after tRR to address b0, a different (non-adjacent) bank than the
REFA command.
A second ACT command can be sent after a time tRC to address c0, the same bank (or an adjacent bank) as the
REFA command.
Note that a broadcast REFP command is issued a time tRAS after the initial REFA command in order to precharge
the refreshed bank in all RDRAMs. After a bank is given a REFA command, no other core operations(activate or
precharge) should be issued to it until it receives a REFP.
It is also possible to interleave refresh transactions (not shown). In the figure, the ACT b0 command would be
replaced by a REFA b0 command. The b0 address would be broadcast to all devices, and would be {Broadcast,
Ba+2,REFR}. Note that the bank address should skip by two to avoid adjacent bank interference. A possible bank
incrementing pattern would be: {12, 10, 5, 3, 0, 14, 9, 7, 4, 2, 13, 11, 8, 6, 1, 15, 28, 26, 21, 19, 16, 30, 25, 23, 20, 18,
29, 27, 24, 22, 17, 31}. Every time bank 31 is reached, a REFA command would automatically increment the REFR
register.
A second refresh mechanism is available for use in PDN and NAP power states. This mechanism is called self-
refresh mode. When the PDN power state is entered, or when NAP power state is entered with the NSR control
register bit set, then self-refresh is automatically started for the RDRAM.
Self-refresh uses an internal time base reference in the RDRAM. This causes an activate and precharge to be
carried out once in every tREF / 2 ^BBIT+RBIT interval. The REFB and REFR control registers are used to keep track of the
bank and row being refreshed.
Before a controller places an RDRAM into self-refresh mode, it should perform REFA/REFP refreshes until the bank
address is equal to the maximum value. This ensures that no rows are skipped. Likewise, when a controller returns
an RDRAM to REFA/REFP refresh, it should start with the minimum bank address value (zero).
Figure 24-2 illustrates the requirement imposed by the tBURST parameter. After PDN or NAP (when self-refresh is
enabled) power states are exited, the controller must refresh all banks of the RDRAM once during the interval tBURST
after the restricted interval on the ROW and COL buses. This will ensure that regardless of the state of self-refresh
during PDN or NAP, the tREF, MAX parameter is met for all banks. During the tBURST interval, the banks may be
refreshed in a single burst, or they may be scattered throughout the interval. Note that the first and last banks to be
refreshed in the tBURST interval are numbers 12 and 31, in order to match the example refresh sequence.
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Data Sheet E0251N20 (Ver. 2.0)