BCM43907 Datasheet, PDF (66/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
GPIO Signals and Strapping Options
Section 10: GPIO Signals and Strapping
Options
Overview
This section describes GPIO signals and strapping options. The pins are sampled at power-on reset (POR) to
determine various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion
of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in Table 12 on
page 67. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the
default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground, using
a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Weak Pull-Down and Pull-Up Resistances
At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak pull-down resistances (for a pin voltage of
VDDO) are 37.99 kΩ, 44.57 kΩ, and 51.56 kΩ, respectively. At VDDO = 3.3V ±10%, the minimum, typical, and
maximum weak pull-up resistances (for a pin voltage of 0V) are 34.73 kΩ, 39.58 kΩ, and 44.51 kΩ, respectively.
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 65