BCM43907 Datasheet, PDF (100/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
Interface Timing and AC Characteristics
Section 17: Interface Timing and AC
Characteristics
Ethernet MAC (MII/RMII) Interface Timing
MII Receive Packet Timing
Figure 17 and Table 39 provide the MII receive packet timing.
Figure 17: MII Receive Packet Timing
RXC
t402
t404
t401
t403
RXDV
RXD[3:0]
Parameter
t401
t402
t403
t404
–
Table 39: MII Receive Packet Timing Parameters
Description
Minimum Typical
RXDV and RXD[3:0] to RXC rising setup time 10
–
RXC clock period (10BASE-T mode)
–
400
RXC clock period (100BASE-TX mode)
–
40
RXC low/high time (10BASE-T mode)
160
–
RXC low/high time (100BASE-TX mode) 16
–
RXDV and RXD[3:0] to RXC rising hold time 10
–
Duty cycle
40
50
Maximum Units
–
ns
–
ns
–
ns
240
ns
24
ns
–
ns
60
%
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 99