BCM43907 Datasheet, PDF (120/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
USB PHY Electrical Characteristics and Timing
USB 2.0 Timing Diagrams
Figure 36 shows the important timing parameters associated with a post-reset transition to high-speed (HS)
operation.
Figure 36: USB 2.0 Bus Reset to High-Speed Mode Operation
< 100 μs
40 to 60 μs
100 to 500 μs
DP Idle
DM Idle
3 to 3.125 ms
Device
K-Chirp
> 1.0 ms
< 7 ms
100 to
875 μs
> 10 ms
Start of
Reset
Device Goes
into Full-
Speed Mode
Start of Host
(Hub) Chirp
Device Tests for
Single-Ended Zero
(SE0) State
High-
Speed
Chirp
HS Data
HS Data
End of Host
(Hub) Chirp
End of
Reset
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 119