BCM43907 Datasheet, PDF (10/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram................................................................................................................... 2
Figure 2: Block Diagram and I/O...................................................................................................................... 15
Figure 3: Typical Power Topology (Page 1 of 2).............................................................................................. 19
Figure 4: Typical Power Topology (Page 2 of 2).............................................................................................. 20
Figure 5: Recommended Oscillator Configuration ........................................................................................... 24
Figure 6: Recommended Circuit to Use With an External Reference Clock .................................................... 25
Figure 7: Signal Connections to an SDIO Host (SD 4-Bit Mode) ..................................................................... 35
Figure 8: Signal Connections to an SDIO Host (SD 1-Bit Mode) ..................................................................... 35
Figure 9: Topology of the USB 2.0 Core ......................................................................................................... 38
Figure 10: BCM43907 Configured as a DRD + USB 2.0 PHY......................................................................... 40
Figure 11: Broadcom 2-Wire External Coexistence Interface.......................................................................... 42
Figure 12: WLAN MAC Architecture ................................................................................................................ 45
Figure 13: WLAN PHY Block Diagram............................................................................................................. 50
Figure 14: Radio Functional Block Diagram .................................................................................................... 52
Figure 15: 316-Bump WLCSP Map ................................................................................................................. 53
Figure 16: Port Locations for WLAN Testing ................................................................................................... 79
Figure 17: MII Receive Packet Timing ............................................................................................................. 99
Figure 18: MII Transmit Packet Timing .......................................................................................................... 100
Figure 19: RMII Receive Packet Timing ........................................................................................................ 101
Figure 20: RMII Transmit Packet Timing ....................................................................................................... 102
Figure 21: I²S Master Mode Transmitter Timing ............................................................................................ 103
Figure 22: I²S Slave Mode Receiver Timing.................................................................................................. 103
Figure 23: I²S Frame-Level Timing ................................................................................................................ 104
Figure 24: SDIO Bus Timing (Default-Speed Mode)...................................................................................... 105
Figure 25: SDIO Bus Timing (High-Speed Mode).......................................................................................... 106
Figure 26: SDIO Clock Timing (SDR Modes) ................................................................................................ 107
Figure 27: SDIO Bus Input Timing (SDR Modes) .......................................................................................... 108
Figure 28: SDIO Bus Output Timing (SDR Modes up to 50 MHz) ................................................................. 109
Figure 29: S/PDIF Interface Timing ............................................................................................................... 110
Figure 30: S/PDIF Data Output Timing .......................................................................................................... 110
Figure 31: SPI Flash Read-Register Timing .................................................................................................. 112
Figure 32: SPI Flash Write-Register Timing .................................................................................................. 113
Figure 33: Memory Fast-Read Timing ........................................................................................................... 114
Figure 34: Memory-Write Timing ................................................................................................................... 115
Figure 35: SPI Flash Timing Parameters Diagram ........................................................................................ 116
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
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