BCM43907 Datasheet, PDF (102/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
Ethernet MAC (MII/RMII) Interface Timing
RMII Receive Packet Timing
Figure 19 and Table 41 provide the RMII receive packet timing.
Figure 19: RMII Receive Packet Timing
REF_CLK
CRS_DV
RXD[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X X X X X X 0
RXD[0] 0 0 0 0 0 0 0 1 1 1 1 1 1 1 X X X X X X 0
/J/
/K/
Preamble
SFD
Data
Table 41: RMII Receive Packet Timing
Parameter
Symbol Minimum Typical Maximum Unit
REF_CLK Cycle Time
–
RXD[1:0], RXER, CRS_DV Output delay from –
REF_CLK rising
Notes:
–
20
–
ns
2
–
10
ns
1. In 10 Mbps mode, there are ten REF_CLK periods per data period.
2. The receiver accounts for differences between the local REF_CLK and the recovered clock through use of
sufficient elasticity buffering.
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 101