BCM43907 Datasheet, PDF (107/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
SDIO Interface Timing
SDIO High-Speed Mode Timing
SDIO high-speed (HS) mode timing is shown by the combination of Figure 25 and Table 46.
Figure 25: SDIO Bus Timing (High-Speed Mode)
50% VDD
SDIO_CLK
f_PP
t_WL
t_WH
Input
t_THL
t_ISU
t_TLH
t_IH
Output
t_ODLY
t_OH
Table 46: SDIO Bus Timing^a Parameters (High-Speed Mode)
Parameter
Symbol Minimum Typical Maximum Unit
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VIL^b
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
Clock high time
Clock rise time
Clock low time
fPP
0
–
50
fOD
0
–
400
tWL
7
–
–
tWH
7
–
–
tTLH
–
–
3
tTHL
–
–
3
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
6
–
–
tIH
2
–
–
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
tODLY –
–
14
Output hold time
tOH
2.5
–
–
Total system capacitance (each line)
CL
–
–
40
a. Timing is based on CL  40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 106