BCM43907 Datasheet, PDF (112/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
S/PDIF Interface Timing
Table 50 provides the S/PDIF biphase mark code timing parameters (to be used in conjunction with Figure 30
on page 110).
Parameter
–
–
Table 50: SPDIF Biphase Mark Code Timing Parameters
Symbol
t_CLK
t_CR, t_CF
Minimum
40
–
Maximum
–
0.3 × t_CLK
Unit
ns
ns
Comments
192 kHz sample rate
–
Duty cycle –
30
70
%
–
Table 51 provides the S/PDIF biphase mark code sample rate and receiver clock frequency.
Table 51: SPDIF Biphase Mark Code Sample Rate and Receiver Clock Frequency
Parameter
Sampling
frequency
Component
clock
frequency
Symbol
f_S
f_CLOCK
Minimum
–
–
Maximum
192
25
Unit
kHz
MHz
Comments
192 kHz sample rate maximum.
Typical is 128 × f_S, max is 192 × f_S.
Clock is 2× the desired data rate or
2 × 192 kHz × 64 = 24.576 MHz.
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 111