BCM43907 Datasheet, PDF (104/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
I²S Master and Slave Mode TX Timing
I²S Master and Slave Mode TX Timing
Figure 21 and Table 43 on page 103 provide the I²S Master mode transmitter timing.
Figure 21: I²S Master Mode Transmitter Timing
t _RC
I2S_SCLK
I2S_SDATO
and I2S_LRCK
T
thtr _{= 0}
t _{dtr = 0.8T}
t _{LC = 0.35T}
T = Clock period.
T_tr = Minimum allowed clock period for transmitter.
T > T_tr.
t_RC is only relevant for transmitters in Slave mode.
t _{HC = 0.35T}
Figure 22 and Table 43 on page 103 provide the I²S Slave mode receiver timing.
Figure 22: I²S Slave Mode Receiver Timing
VH _{= 2.0V}
V _{L = 0.8V}
T
I2S_SCLK
I2S_SDATAI
and I2S_LRCK
tLC = 0.35T
tsr = 0.2T
T = Clock period.
T_r = Minimum allowed clock period for the transmitter.
T > T_r.
tHC = 0.35T
thr = 0
VH _{= 2.0V}
V _{L = 0.8V}
Parameter
Clock period T
Slave mode:
Table 43: Timing for I²S Transmitters and Receivers
Transmitter
Receiver
Lower Limit
Upper Limit
Lower Limit
Minimum Maximum Minimum Maximum Minimum Maximum
T_tr
–
–
–
T_tr
–
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March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 103