BCM43907 Datasheet, PDF (111/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
S/PDIF Interface Timing
S/PDIF Interface Timing
The S/PDIF protocol embeds the clock and data within a stream of data using a Biphase Mark Code (BMC).
Figure 29 shows the S/PDIF interface timing.
Figure 29: S/PDIF Interface Timing
Clock
Data
Encoded (BMC)
1
0
0
1
1
0
1
0
0
1
0
Figure 30 shows the S/PDIF data output timing.
Figure 30: S/PDIF Data Output Timing
t_CLK
SPDIF_OUT
t_CR
t_CF
t_CR
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
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