BCM43907 Datasheet, PDF (106/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
SDIO Interface Timing
SDIO Interface Timing
SDIO Default-Speed Mode Timing
SDIO default-speed (DS) mode timing is shown by the combination of Figure 24 and Table 45.
Figure 24: SDIO Bus Timing (Default-Speed Mode)
fPP
tWL
tWH
SDIO_CLK
Input
tTHL
tTLH
tISU
tIH
Output
t_ODLY
(max)
t_ODLY
(min)
Table 45: SDIO Bus Timing^a Parameters (Default-Speed Mode)
Parameter
Symbol Minimum Typical Maximum Unit
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VIL^b
Frequency – Data Transfer mode
Frequency – Identification mode
Clock low time
Clock high time
Clock rise time
fPP
0
–
25
fOD
0
–
400
tWL
10
–
–
tWH
10
–
–
tTLH
–
–
10
Clock low time
tTHL
–
–
10
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
5
–
–
tIH
5
–
–
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
tODLY 0
–
14
Output delay time – Identification mode
tODLY 0
–
50
a. Timing is based on CL  40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 105