BCM43907 Datasheet, PDF (124/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
Sequencing of Reset and Regulator Control Signals
Control Signal Timing Diagrams
Figure 39: REG_ON = High, No HIB_REG_ON_OUT Connection to REG_ON
32.678 kHz
Sleep Clock
VBAT
VDDIO
REG_ON
HIB_REG_ON_IN
~ 2 Sleep Cycles
Figure 40: HIB_REG_ON_IN = High, HIB_REG_ON_OUT Connected to REG_ON
32.678 kHz
Sleep Clock
VBAT
VDDIO
HIB_REG_ON_IN
~ 2 Sleep Cycles
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 123