BCM43907 Datasheet, PDF (114/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
SPI Flash Timing
Write-Register Timing
Figure 32 shows the SPI flash extended and quad write-register timing.
Note: Regarding Figure 32:
1. All write-register commands except Write Lock Register are supported.
2. The waveform must be extended for each protocol: to 23 for extended and five for quad.
3. A Write Nonvolatile Configuration Register operation requires data being sent starting from the least significant byte.
Figure 32: SPI Flash Write-Register Timing
Extended
0
C
DQ0
Command
MSB
7
8
LSB
D_IN
MSB
9
D_IN
10
11
12
13
14
15
LSB
D_IN
D_IN
D_IN
D_IN
D_IN
D_IN
D_IN
Quad
0
C
DQ[3:0]
Command
MSB
1
2
LSB
D_IN
MSB
3
LSB
D_IN
D_IN
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 113