BCM43907 Datasheet, PDF (105/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
I²S Master and Slave Mode TX Timing
Table 43: Timing for I²S Transmitters and Receivers
Transmitter
Receiver
Lower Limit
Upper Limit
Lower Limit
Parameter
Clock HIGH, t_HC
Clock LOW, t_LC
Clock rise time, t_RC
Transmitter delay, t_dtr
Transmitter hold time, t_htr
Receiver setup time, t_sr
Receiver hold time, t_hr
Minimum
–
–
–
–
0
–
–
Maximum Minimum Maximum Minimum Maximum
0.35T_r
–
–
–
0.35T_r
–
–
–
–
0.15T_tr
–
–
–
–
0.8T
–
0.35T_r
0.35T_r
–
–
–
–
–
–
–
–
–
–
–
0.2T_r
–
–
–
–
0
Table 44 provides the I2S_MCLK specification.
Table 44: I2S_MCLK Specification
Parameter
Minimum
Frequency range
1
Frequency accuracy (with respect to the XTAL frequency) –
Tuning resolution
–
Tuning range
–
Tuning step size
–
Tuning rate
–
Baseband jitter (100 Hz to 40 kHz)
–
Wideband jitter (100 Hz to 1 MHz)
–
Typical
–
1
50
1000
–
1
–
–
Maximum
40
–
–
–
10
–
100
200
Unit
MHz
ppb
ppb
ppm
ppm
ppm/ms
ps rms
ps rms
Figure 23 shows the I²S frame-level timing.
Figure 23: I²S Frame-Level Timing
I2S_LRCLK
I2S_SCLK
I/O Data
Left Channel
1/fs
Right Channel
1 clock
123
MSB
n–2 n–1 n
LSB
1 clock
123
MSB
n–2 n–1 n
LSB
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March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
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