BCM43907 Datasheet, PDF (32/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
I²S
• I²S master clock: I2S_MCLK0
The following signals apply to the second I²S interface:
• I²S bit clock: I2S_SCLK1 (sometimes referred to as I2S_BITCLK)
• I²S word select: I2S_LRCK1 (sometimes referred to as I2S_WS)
• I²S serial data out: I2S_SDATAO1
• I²S serial data in: I2S_SDATAI1
• I²S master clock: I2S_MCLK1
I2S_SDATAO0 and I2S_SDATAO1 are outputs.
I2S_MCLK, I2S_SCLK and I2S_LRCLK can be configured as either inputs or outputs depending on whether the
master clock source is on- or off-chip and whether the I²S is operating in Slave or Master mode.
Channel word lengths of 16 bits, 20 bits, 24 bits, and 32 bits are supported, and the data is justified so that the
MSB of the left-channel data is aligned with the MSB of the I²S bus, per the I²S specification. The MSB of each
data word is transmitted one bit-clock cycle after the I2S_LRCK transition, synchronous with the falling edge of
the bit clock. Left-channel data is transmitted when I2S_LRCK is low, and right-channel data is transmitted when
I2S_LRCK is high. An embedded 128 × 32-bit single-port SRAM for data processing enhances the performance
of the interface.
An audio PLL generates an internal master clock (for I2S_MCLK0 and I2S_MCLK1) that provides support for
various sampling rates.
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 31