BCM43907 Datasheet, PDF (65/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
Signal Descriptions
Table 10: Signal Descriptions (Cont.)
Bump Number Signal Name
Type Description
SPI Interfaces
Note: Each SPI interface can alternatively be configured and used as a BSC interface.
76
SPI0_CLK
O SPI clock
78
SPI0_MISO
I
SPI data master in
81
SPI0_SISO
O SPI data master out
82
SPI0_CS
O SPI slave select
83
SPI1_CLK
O SPI clock
84
SPI1_MISO
I
SPI data master in
86
SPI1_SISO
O SPI data master out
80
SPI1_CS
O SPI slave select
UART Interface
85
UART0_CTS
I
UART clear-to-send
91
UART0_RTS
O UART request-to-send
88
UART0_RXD
I
UART serial input
87
UART0_TXD
O UART serial output
USB 2.0
170
USB2_DM
I/O USB 2.0 data
167
USB2_DP
I/O USB 2.0 data
169
USB2_RREF
I
USB 2.0 reference resistor connection
175
USB2_MONCDR
O USB 2.0 CDR monitor
184
USB2_MONPLL
O USB 2.0 PLL monitor
165
USB2_DSEL
I
USB 2.0 host and device mode selection
Voltage Regulators (Integrated)
108, 113, 122, 125 SR_VDDBAT5V
I
98, 99, 101, 102, SR_VLX
O
109, 112
115, 116, 120, 127 LDO_VDD1P5
I
128, 129
LDO_VDDBAT5V
I
221
WRF_XTAL_VDD1P35 I
220
WRF_XTAL_VDD1P2 O
106
VOUT_LNLDO
O
114, 121, 126
VOUT_CLDO
O
118, 119
VOUT_3P3
O
117
VOUT_3P3_SENSE O
103
VOUT_CLDO_SENSE O
107
VOUT_BBPLLOUT O
VBAT.
CBUCK switching regulator output
LNLDO input
LDO VBAT
XTAL LDO input (1.35V)
XTAL LDO output (1.2V)
Output of LNLDO
Output of core LDO
LDO 3.3V output
Voltage sense pin for LDO 3.3V output
Voltage sense pin for core LDO
Output of baseband PLL
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 64