BCM43907 Datasheet, PDF (110/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
SDIO Interface Timing
Device Output Timing
SDIO device output timing in the SDR modes with clock rates up to 50 MHz is shown by the combination of
Figure 28 and Table 49.
Figure 28: SDIO Bus Output Timing (SDR Modes up to 50 MHz)
t_CLK
SDIO_CLK
t_ODLY
t_OH
CMD input
DAT[3:0] input
Symbol
t_ODLY
t_OH
Table 49: SDIO Bus Output Timing Parameters (SDR Modes up to 50 MHz)
Minimum
–
1.5
Maximum Unit
14.0
ns
–
ns
Comments
t_CLK ≥ 20 ns C_L= 40 pF
Hold time at the t_ODLY (min.) C_L= 15 pF
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 109