BCM43907 Datasheet, PDF (103/128 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

BCM43907 Preliminary Data Sheet
Ethernet MAC (MII/RMII) Interface Timing
RMII Transmit Packet Timing
Figure 20 and Table 42 provide the RMII transmit packet timing.
Figure 20: RMII Transmit Packet Timing
REF_CLK
TX_EN
TXD[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X X X X X X 0
TXD[0] 0 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X 0
Preamble
SFD
Data
Table 42: RMII Transmit Packet Timing Parameters
Parameter
Symbol
Minimum Typical
REF_CLK Cycle Time
–
–
20
TXEN, TXER, TXD[1:0] setup time to
TXEN_SETUP 4
–
REF_CLK rising
TXEN, TXER, TXD[1:0] hold time from
TXEN_HOLD 2
–
REF_CLK rising
Notes:
1. TXD[1:0] provides valid data for each REF_CLK period while TX_EN is asserted.
2. In 10 Mbps mode, there are ten REF_CLK periods per data period.
Maximum Unit
–
ns
–
ns
–
ns
Broadcom^®
March 12, 2016 • 43907-DS104-R
BROADCOM CONFIDENTIAL
Page 102