STC5420 Datasheet, PDF (7/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Pin Name
REF12_N
CLK1_P
CLK1_N
CLK2_P
CLK2_N
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK8K
CLK2K
SRCSW
MPU_MODE0
MPU_MODE1
MPU_MODE2
CS
WR
RD
ALE/SCLK
RDY
Pin #
43
34
35
36
37
88
89
90
93
94
95
30
31
18
60
59
58
70
71
72
73
75
STC5420
Synchronous Clock for SETS
Data sheet
Table 1: Pin Description
I/O
Description
I Differential reference input 12 negative(LVPECL/LVDS)
O Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₁
LVPECL or LVDS
O Clock output CLK1 negative, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₁
LVPECL or LVDS
O Clock output CLK2 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₂
LVPECL or LVDS
O Clock output CLK2 negative. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₂
LVPECL or LVDS
O Clock output CLK3. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₃ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz or proprietary composite signal from Synthesizer F. LVCMOS.
O Clock output CLK4. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₄ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz or proprietary composite signal from Synthesizer F. LVCMOS.
O Clock output CLK5. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₅, or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz or proprietary composite signal from Synthesizer F. LVCMOS.
O Clock output CLK6. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₆ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz, or proprietary composite signal from Synthesizer F. LVCMOS.
O Clock output CLK7. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₇ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz, or proprietary composite signal from Synthesizer F. LVCMOS.
O Clock output CLK8. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₈ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz, or proprietary composite signal from Synthesizer F. LVCMOS.
O 8kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0)
O 2kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0)
I Hard-wired manual reference pre-selection
I Bus interface: Intel, Motorola, Multiplex, SPI
I
I
I SPI bus chip select
I Write access for Intel, Motorola and Multiplex bus interface
I Read access for Intel and Multiplex bus interface
I ALE: Address latch enable for Multiplex bus interface
SCLK: Clock edge selection for SPI
O Ready/Data Acknowledge for Intel, Motorola and Multiplex bus interface
Page 7 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011