STC5420 Datasheet, PDF (36/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
Register Descriptions and Operation
General Register Operation
The STC5420 device has 1, 2, 3, and 4 byte registers. One-byte registers are read and written directly. Multiple
-byte registers must be read and written in a specific manner and order, as follows:
Multibyte register reads
A multi byte register read must commence with a read of the least significant byte first. This triggers a latch of
the remaining byte(s) to a holding register, ensuring that the remaining data will not change with the continuing
operation of the device. The remaining byte(s) must be read consecutively with no intervening read/writes
from/to other registers.
Multibyte register writes
A multi byte register write must commence with a write to the least significant byte first. Subsequent writes to
the remaining byte(s) must be performed in ascending byte order, consecutively, with no intervening read/
writes from/to other registers, but with no timing restrictions. Multibyte register writes are temporarily stored in
a holding register, and are transferred to the target register when the most significant byte is written.
Chip_ID, 0x00 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x00
0x01
0x20
0x54
Indicates chip’s ID number
Chip_Rev, 0x02 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x02
Revision Number
Indicates the revision number of STC5420
Chip_Sub_Rev, 0x03 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x03
Sub-Revision Number
Indicates the firmware revision number of STC5420
T0_MS_Sts, 0x04 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x04
Not used
T0 M/S
Indicates the T0 timing generator operating in master or slave mode.
This state is selected by pin MC_SL. 1 = Master, 0 = slave
Page 36 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011