STC5420 Datasheet, PDF (26/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
at the register Synth Index Select, Synth Freq
Value, and Synth Skew Adj. Output frequency is
programmable from 1MHz to 156.25MHz, in 1kHz
steps.
CLK3~CLK8 is selected when associated synthesizer
G₃~G₈, or G_T4 is selected at the register CLK(3~8)
Sel. Output frequencies or phase skew of
CLK3~CLK8 are programmable when frequency or
skew of the associated synthesizer is programmed at
the register Synth Index Select, Synth Freq Value,
and Synth Skew Adj. Output frequency of
CLK3~CLK8 is programmable from 1MHz to
156.25MHz, in 1kHz steps, via either synthesizer
G₃~G₈ or G_T4 individually. CLK3~CLK8 can also out-
put frame pulse clocks when synthesizer F is selected
at the register CLK(3~8) Sel. One of frame pulse
clock of Frame8K, Frame2K, or proprietary composite
signal is selected at the register Frame Mux for
CLK3~CLK8 individually. Phase skew of frame pulse
clocks is programmable simultaneously at the register
Synth Index Select and Synth Skew Adj.
Redundant Application
Timing generator T0 supports master/slave and multi-
ple-master operation for redundant applications to
allow system protection against single part failure.
External Frame Reference Input
For redundant design, either in master/slave mode or
multiple-master mode, all the timing devices should
keep in frame phase alignment. In order to achieve
the alignment, the frame edge of reference input is
required. If the reference input is not proprietary com-
posite signal or 8kHz input signal which contains its
own frame information, an external frame reference
input (at pin EX_SYNC) is used and some configura-
tion enhancements are required. See register Slave
Frame Align for slave mode configuration (when pin
MC/SL = 0). See register Master Frame Align for
master mode configuration (when pin MC/SL = 1).
Master Slave Configuration
Pairs of STC5420 devices may be operated in a
master/slave configuration. Pin MC/SL determines
each T0 timing generator of the two devices to work
in master mode or slave mode. In master/slave
configuration, slave device synchronizes and frame
phase aligns with the master device and reverts to
lock to the same external reference that the master
device was locked to, using 100Hz loop bandwidth
and ignores the loop bandwidth programmed at regis-
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slave frame phase alignment, two signals (one cross
reference clock and one frame reference clock) or
one signal (contains both cross reference and frame
reference clock) is interconnected between the
master and slave. The combination of cross refer-
ence and frame reference clock has four options:
1. High frequency output of master device feeds into
REF7 of slave device as cross reference; Frame
pulse 8kHz or 2kHz output of master device
feeds into EX_SYNC of slave device as frame
reference.
2. Frame pulse 8kHz output of master device feeds
into EX_SYNC of slave device as cross reference
and frame reference.
3. Proprietary composite signal of master device
feeds into REF7 of slave device as cross refer-
ence and frame reference.
4. Proprietary composite signal of master device
feeds into EX_SYNC as cross reference clock
and frame reference.
To achieve 2kHz frame alignment, option 1, 3, or 4
should be selected. 8kHz on EX_SYNC pin cannot
produce 2kHz frame alignment. See register Slave
Frame Align for cross reference clock and frame
reference clock selection details. If an error occurs
when sampled on the selected frame edge of the
cross reference, bit FEE of register PLL Status will
be asserted. Master’s frame pulse output CLK8K
replace the selected frame reference input as the
temporary frame reference. This error does not send
alarm of synchronization faliure or loss of lock. User
can invoke a relock event to PLL by programming the
register PLL Event In. The frame edge is re-selected
as well.
User can select either falling edge or rising edge for
frame reference input EX_SYNC when the frame
reference input on pin EX_SYNC is not composite
signal. See the register EX SYNC Edge Config.
The proprietary composite signal contains not only
cross reference clock and the frame reference clock
of the master device but the information of the
selected reference of the master device. Having this
information, the slave unit is able to identify the
selected reference of the master device. Therefore, in
automatic reference selection mode, when the slave
device takes it over to be the new master device, it
can select the reference clock which previous master
device was locked to by setting bit Slave Inherit Mode
Page 26 of 70 Rev: 2.0
Date: September 28, 2011
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