STC5420 Datasheet, PDF (68/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
2.0
Update Funtional diagram
Remove LVCMOS level for REF11 and REF12
Add register Frame_Mux and Diff_Ref_Polarity
Change register CLK8K_Sel and CLK2K_Sel to Frame8K_Sel and CLK2K_Sel
Change name of register Ref_Freq to Ref_Acceptable_Freq
Add description of frame mux
Update CLK3~CLK8, CLK8K and CLK2K detail diagram in Figure 6, 7
Rephase Master Slave Configuration
Correct SDI of SPI Bus Timing, Write access
Correct t_CH and t_CL, LSB to MSB and MSB to LSB in serial bus timing figure
Correct Min value of t_CH and t_CL to 50ns in serial bus timing table
Correct description of t_CSHLD and t_CSTRI in serial bus timing table
Update register Ref_Info Interrupt_Event_Sts, PLL_Event_Out, PLL_Event_In,
CLK(3~8)_Sel, Synth_Index_Select, Synth_Freq_Value, Synth_Skew_Adj
Update order information
Add section of Specification Modification
Miscellaneous
1
1, 13, 16, 22
11, 57, 58
11, 56
13, 22, 57
25, 26,
25, 26
26
29
28, 29
29
29
40, 48, 52, 53, 54, 55, 56
63
64
All pages
Page 68 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011