STC5420 Datasheet, PDF (27/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
of the register Control Mode. However, if the new
master device operates in revertivity mode or has
different qualification results than previous master
device, it will select any preferred reference input.
In master/slave mode, for the latency delay on the
cross-couple path, it may be compensated up and
down 3.2µs, in 0.1ns step. This will then minimize the
phase hits to the downstream devices resulting from
master/slave switches.
Multiple Master Configuration
In multiple-master configuration, every unit works as
master and locks to the same reference input. Each
unit has consistent loop bandwidth settings. To
achieve frame phase alignment for all the masters’
outputs, each device has to choose same frame edge
on the selected reference input clock. The system
may provides every master a common extra frame
reference or simply choose a 8kHz reference input.
Frame reference clock and frame edge on each refer-
ence input is configured at register Master Frame
Align. If an error occurs when sampled on the
selected frame edge of the selected reference, bit
FEE of register PLL Status will be asserted and
frame pulse output CLK8K replaces the selected
frame reference input as the temporary frame refer-
ence. This error does not send alarm of synchroniza-
tion faliure or loss of lock. User can invoke a re-lock
event to PLL by programming the register PLL Event
In. The frame edge is re-selected as well.
Multiple master configuration works only in frame
phase align mode. By writing to the Master Frame
Align register, user can set T0 timing generator to
frame phase align mode with the frame edge selec-
tion.
To meet the same synchronization and frame align-
ment requirements, each unit should keep the same
parameter setup, especially loop bandwidth. Multiple-
master mode demands a high quality external oscilla-
tor to obtain a precise frame phase alignment.
Event Interrupts
The STC5420 events shown following below are
interrupt events might occurred.
- Qualification status of the reference inputs change
- Activity status of the cross reference inputs change
- Selected reference of timing generator T0 changes in
automatic reference_Fs_uel_nec_cti_to_in_{onal Specification}
- Selected reference of timing generator T4 changes in
automatic reference selection
- PLL status of timing generator T0 changes
- PLL status of timing generator T4 changes
- Out-Event of timing generator T0 asserts
- Out-Event of timing generator T4 asserts
The interrupt events can be read from Interrupt Sta-
tus register. Each bit indicates one events. The asso-
ciate bit of the Interrupt Status will not be changed
automatically when the event is cleared. Therefore,
the user need write ‘1’ to the associate bit to erase
the event.
The STC5420 has a pin EVENT_ INTR (pin 8) for
indicating the event interrupt occurrence. The pin
may be wired to user’s micro-controller. User can pro-
gram the Interrupt Mask register to decide which of
interrupt events will send an alarm to the micro-con-
troller by asserting the EVENT_INTR pin. User can
program at the Interrupt Configuration register to
specify the logic level (active high or low) of the pin
EVENT_INTR when it’s trigged by the interrupt event.
User may also program the Interrupt Configuration
register to define pin states as tri-state or logic inac-
tive when no interrupt event occurs.
Field Upgradability
The STC5420 supports field upgradability which
allows the user to load size of 7600 byte firmware
configuration data (provided as per request) via bus
interface. Field upgrade can only be performed at
least 3ms after reset.
1. User may read Bit READY of the register Field
Upgrade Status to check if field upgrade is ready to
start.
2. To begin the field upgrade, write to register Field
Upgrade Start three times consecutively, with no inter-
vening read/writes from/to other registers, see the reg-
ister Field Upgrade Start for details.
3. Once the field upgrade process begins, the STC5420
is hold for data loading. Write 7600 bytes firmware con-
figuration data to the register Field Upgrade Data one
byte at a time to complete data loading. User can read
the same register for the written byte. But regardless of
how many times the user read, only the last written
byte will be read from the register.
4. Read the register Field Upgrade Count for how many
bytes of configuration data has been loaded. Bit
Load_Compelet of the register Field Upgrade Status
Page 27 of 70 Rev: 2.0
Date: September 28, 2011
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice