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STC5420 Datasheet, PDF (55/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS
Default value: 0
Register
Frame_Mux
(Bit5~Bit4)
X
0
1
2
3
X
CLK6_Sel, 0x56 (R/W)
Register
CLK5_Sel
(Bit1~Bit0)
1
2
2
2
2
3
STC5420
Synchronous Clock for SETS
Data sheet
CLK5 Synthesizer Select
Synthesizer G4 (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK5 tie to ground
Synthesizer GT4 (T4)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x56
Not used
CLK6 Synthesizer Select
Selects the clock output CLK6 derived from synthesizer G6 (T0), synthesizer F or synthesizer GT4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit7~bit6 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or Frame2K.
Signal level of CLK6 is LVCMOS.
Register
Frame_Mux
(Bit7~Bit6)
X
X
0
1
2
3
X
Default value: 0
CLK7_Sel, 0x57 (R/W)
Register
CLK6_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
CLK6 Synthesizer Select
Put CLK6 in tri-state mode
Synthesizer G4 (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK6 tie to ground
Synthesizer GT4 (T4)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x57
Not used
CLK7 Synthesizer Select
Selects the clock output CLK7 derived from synthesizer G7 (T0), synthesizer F or synthesizer GT4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit9~bit8 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or Frame2K.
Signal level of CLK7 is LVCMOS.
Page 55 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011