STC5420 Datasheet, PDF (1/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
Description
Features
Functional Specification
The RoHS 6/6 compliant STC5420 is a single chip clock
synchronization solution for applications in SDH/SETS,
SONET, and Synchronous Ethernet network elements. The
device is fully compliant with ITU-T G.813 option 1 and 2,
G.8262 EEC Opt1 and Opt2 and Telcordia GR1244 and
GR253.
The STC5420 accepts 12 clock reference inputs and gener-
ates 10 synchronized clock outputs: CLK1~CLK8, frame
pulse clock CLK8K at 8kHz, and frame pulse clock CLK2K
at 2kHz. CLK1~CLK8 may be programmed for wide variety
of frequencies from 1MHz up to 156.25MHz, in 1kHz steps.
Reference inputs are individually monitored for activity and
quality. Reference selection may be automatic, manual, and
hard-wired manual.
Two independent timing generators, T0 and T4, may oper-
ate in the Freerun, Synchronized, Pseudo Holdover, and
Holdover mode. Each timing generator includes a DSP-
based PLL. Synchronized mode external timing while fre-
erun and holdover mode are self-timing. T0 supports Mas-
ter/Slave and Multiple Master operation for redundant
design. T4 only supports master operation. DSP-based PLL
technology removes any external component except the
oscillator. It provides excellent performance and reliability to
STC5420.
The STC5420 is clocked by an external oscillator (TCXO or
OCXO). Using a well-chosen external oscillator ensures the
STC5420 meet the required specification and standards.
- Complies with ITU-T G.813 Opt1/Opt2, G.8262 EEC
Opt1/Opt2, Telcordia GR1244 and GR253 (Stratum3/4E/
4/SMC)
- Two timing generators T0 and T4; T4 may lock to T0’s
synchronized output
- Supports Master/Slave and Multiple-Master redundant
application (T0 timing generator only)
- Provides programmable compensation for phase delay
between master and slave unit, in 0.1ns steps
- Accepts external oscillator at frequency of 10MHz,
12.8MHz, 19.2MHz,or 20MHz with programming
- Accepts 12 clock reference inputs
- Supports frequency auto detection or manually accept-
able frequency for reference inputs. Each of them is
monitored for activity and quality
- Automatic/manual/hard-wired manual reference select
- Outputs 10 synchronized clock outputs, including 2
frame pulse clocks CLK8K and CLK2K
- 10 clock synthesizers generate frequencies
- Programmable phase skew in synthesizer level
- Phase-align or hit-less reference locking/switching
- Programmable loop bandwidth, from 0.1Hz to 100Hz
- Supports bus interface: Intel, Motorola, Multiplex, SPI
- Single 3.3V operation
- IEEE 1149.1 JTAG boundary scan
- Available in TQFP100 package
SRCSW
Master_Slave
EX_SYNC
Ref Clk
12
10 LVCMOS
+
2 LVPECL/LVDS
TCXO
OCXO
2
T0 Timing
Generator
Synthesizer G₁
Synthesizer G₂
Synth
F
Frame8K
Frame2K
Composite
Synthesizer G₃
Synthesizer G₄
Ref
Monitor
Synthesizer G₅
Synthesizer G₆
Synthesizer G₇
T4 Timing
Generator
Synthesizer G₈
Synthesizer G_T4
µP Interface
Figure 1:Functional Block Diagram
CLK1, LVPECL/LVDS
CLK2, LVPECL/LVDS
CLK8K
CLK2K
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
Page 1 of 70 TM112 Rev: 2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011