STC5420 Datasheet, PDF (51/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Bits 3 ~ 2
Bits 7 ~ 6
3
Default value: 0
Synth_Index_Select, 0x4A (R/W)
STC5420
Synchronous Clock for SETS
Data sheet
Frame Edge Select
Frame phase align mode, selects
selected reference’s rising edge
next to the frame pulse on the
external frame reference
Address
Bit7
0x4A
Bit6
Bit5
Not Used
Bit4
Bit3
Bit2
Bit1
Bit0
Synthesizer index selection for synthesizer frequency and
phase skew adjustment
Determines which synthesizer is selected for setting frequency value at the register Synth_Freq_Value and
adjusting phase skew at the register Synth_Skew_Adj.
CLK1~CLK8 can be derived from synthesizer G₁~G₈ through T0 path, respectively, in which CLK3~CLK8 can
also be derived from synthesizer F through T0 path or synthesizer G_T4 through T4 path.
Field Value
0
1
2
3
4
5
6
7
8
9
Default value: 0
Synth_Freq_Value 0x4B (R/W)
Synthesizer
Synthesizer F
Synthesizer G₁
Synthesizer G₂
Synthesizer G₃
Synthesizer G₄
Synthesizer G₅
Synthesizer G₆
Synthesizer G₇
Synthesizer G₈
Synthesizer G_T4
Associated CLK Output
CLK8K, CLK2K, CLK3~CLK8
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK3~CLK8
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x4B
0x4C
0x4D
Bits 0-7 of 18 bits Synthesizer Frequency Selection
Bits 15-8 of 18 bits Synthesizer Frequency Selection
Not used
Bits 17-16 of 18 bits Synthesizer
Frequency Selection
Selects synthesizer frequency value from 1MHz to 156.25MHz, in 1kHz steps, for synthesizer G₁~G₈, or G_T4.
Synthesizer is selected at register Synth_Index_Select. CLK1~CLK8 is derived from synthesizer G₁~G₈
through T0 path, respectively, in which CLK3~CLK8 can also be derived from synthesizer F through T0 path or
synthesizer G_T4 through T4 path.
Page 51 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011