STC5420 Datasheet, PDF (32/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
Intel Bus Mode
In Intel mode, the device will interface to 80x86 type processors. The CS, WR, RD, A(0-6), AD(0-7), and RDY
pins are used. Timing is as follows in Figure 13 and Figure 14:
CS
WR
RD
A0-A6
AD0-AD7
RDY
t_RDBs
t_RDB
t_RDB1
t_RDBh
t_As
t_RDYd1
t_Ah
Address
t_Dd1
t_Dd2
Data
t_RDYd2
t_RDY
t_RDYh
t_RDYd3
Figure 13: Intel Bus Read Timing
Table 10: Intel Bus Read Timing
Symbol
t_RDBs
t_RDB
t_RDBh
t_RDB1
t_As
t_Ah
t_Dd1
t_Dd2
t_RDYd1
t_RDYd2
t_RDY
t_RDYh
t_RDYd3
Description
Read setup time
Read low time
Read hold time
Time between consecutive reads
Address setup
Address hold
Data valid delay from RDB low
Data high-z delay from RDB high
CS low to RDY high delay
RD low to RDY low
RDY low time
RD hold after RDY high
RDY high-z delay after CS high
Min
Max
Unit
0
ns
40
ns
0
ns
50
ns
10
ns
0
ns
50
ns
10
ns
13
ns
40
ns
50
ns
0
ns
11
ns
Page 32 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011