STC5420 Datasheet, PDF (67/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Revision History
STC5420
Synchronous Clock for SETS
Data sheet
The following table summarizes significant changes made in each revision. Additions reference current pages.
Revision
0.4
0.4.1
0.5
1.0
1.1
1.2
1.3
Change Description
Preliminary initial issue
Minor releases at Preliminary status
Minor releases at Preliminary status (Completely revised for new design)
First release at final status
Add supported frequency of external oscillator
Add G.8262 EEC option1 and option 2
Correct pin number of SRCSW and AD1 to 18 and 82.
Correct registers address of Master_Frame_Align from 0x63-0x64 to 0x40-0x47
Add register EX_SYNC_Edge_Config and Slave_Frame_Align to Table 2
Correct the description of the register 0x7F in Table 2
Add Master Clock Frequency section
Add Clock Output Jitter section
Remove word “reboot”
Correct description of t_Dd2 in Motorola Bus Read Timing
Correct description of t_Dd1 in Intel Bus Read Timing
Correct CS and RDB to WR in the description of Intel Bus Write Timing
Correct description of t_ALEd of Multiplex Bus Write Timing
Add more detail description to section Chip Master Clock
Add more detail description of the register MCLK_Freq_Reset
Change mechanical specifications due to assembly change
Correct SPI Bus Timing, Write access
Pages
See particular revision
All pages
1
1, 16
7, 8
10
10
11
12
14
19, 27, 56, 57
29
31
32
34
17
57, 58
63
29
Page 67 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011