STC5420 Datasheet, PDF (28/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
will indicate whether the 7600 bytes loading is complete and meanwhile bit CHECKSUM will indicate the loading is
failed or succeed. See register description of Field Upgrade Status for details.
Processor Interface Descriptions
The STC5420 supports four common microprocessor control interfaces: SPI, Motorola, Intel, and Multiplex.
The control interface mode is selected with the MPU_MODE(0/1/2):
MPU_MODE2
(Pin 58)
0
0
0
1
1
MPU_MODE1
(Pin 59)
0
1
1
0
0
MPU_MODE0
(Pin 60)
1
0
1
0
1
Bus Mode
Reserved
Multiplex
Intel
Motorola
SPI
The following sections describe each bus mode’s interface timing:
SPI Bus Mode
The SPI interface bus mode uses the CS, SCLK,SDI, SDO pins, with timing as shown in Figure 8, Figure 9 and
Figure 10. For read operation, serial data output can be read out from the STC5420 on either the rising or fall-
ing edge of the SCLK. The edge selection depends on pin CLKE logic level.
Serial Bus Timing
CS
t_CS
t_CSHLD
t_CSMIN
t_CSTRI
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
t_Ds
t_Dh
t_CL
t_CH
SDI
SDO
1 A0 A1 A2 A3 A4 A5 A6
LSB
MSB
t_DRDY
t_DHLD
D0 D1 D2 D3 D4 D5 D6 ^D7
LSB
MSB
Figure 8:SPI Bus, Read access (Pin CLKE = Low)
Page 28 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011