STC5420 Datasheet, PDF (20/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
tory. This history is accumulated by a built in program-
mable short-term history accumulator consecutively,
which presents the latest updated fractional fre-
quency offset of the synchronous clock output of each
timing generator. The user can read the short-term
history from register Short Term Accu History.
Holdover Mode
Holdover mode is typically used when none of refer-
ence inputs is available and the holdover history has
been built. In holdover mode, the frequency offset of
the clock output is maintained closely to previous
value generated when the selected reference input
was valid. User can select either device holdover his-
tory or user specified holdover history at the register
Con- trol Mode in holdover mode.
PLL Event In
The STC5420 provides direct communication with the
PLL’s timing generator by writing to the register PLL
Event In. Following events can be triggered:
- Relock. PLL starts a relock process if this event is trig-
gered. In frame phase align mode, PLL relocks to the ref-
erence input and the frame edge is re-selected as well.
In phase arbitrary mode, PLL relocks to the reference
input and restart the phase rebuild process.
Frequency and Phase Transients
Severe frequency and phase transients of the clock
output will cause lost of lock or buffer overflow/under-
flow on downstream circuit. By providing programma-
ble maximum slew rate and phase rebuild function,
both frequency and phase transient of the STC5420’s
clock output is controlled to minimize the impact on
downstream circuits.
Frequency Transients
The STC5420 smoothly control the frequency tran-
sient on the clock output. During reference input
switching or operation mode switching (etc., switch to
freerun or holdover mode), if the clock output prior to
switching has different frequency offset than the
desired clock output, it smoothly approaches to
desired frequency offset with a maximum accelera-
tion/decel- eration rate by writing to the register His-
tory Ramp. The maximum slew rate can be
programmed as 1.0, 1.5, 2.0 ppm/second. With a lim-
ited acceleration/ deceleration, the pull-in process
may last longer. However, it will minimize the fre-
quency transient impact to the downstream clock and
ensure meeting components frequency impact toler-
ance.
Functional Specification
Phase Transients
The STC5420 minimize the variation of the phase
transient on the clock output when a phase hit occurs
on the selected reference input. The overshoot in the
clock output’s phase transient response will be a
small amount under 2%.
During reference input switching or recovering from
LOS/LOL condition, the phase transient is also
occurred on the clock output. The STC5420 can mini-
mize it with a phase rebuild function. In synchronized
mode, the phase relationship between the reference
input and the clock output can be programmed to
phase arbitrary or frame phase align at the register
Master Frame Align. If phase arbitrary is selected, a
phase rebuild function is performed before locking to
the new/recovered reference input. Hit-less switching
is achieved with this function and the phase hit to
downstream circuits is eliminated. If frame phase
align is selected, the clock output is in frame phase
alignment with the reference input. Only T0 timing
generator supports frame phase alignment.
History of Fractional Frequency
Offset
The STC5420 monitors and tracks the fractional fre-
quency offset between the clock output and MCLK.
The history data of the frequency offset is used by
clock synthesizers to generate desire outputs while
the timing generator is pending for reference input
availability. Two weighted 3^rd order low-pass filter are
used internally as two history accumulators: the short
term history accumulator and the long term history
accumulator. A mature long term history is stored and
further updated as device holdover history. It is used
when the STC5420 operates in holdover mode. In
addition, the STC5420 allows user to program an
user specified history as needed of the application.
Short-Term History
Short-term history is an average frequency offset
between the clock output and MCLK which is filtered
internally using a weighted 3rd order low-pass filter
with the small time constant. The -3dB filter response
point can be programmed from 0.16Hz to 1.3Hz by
writing to the register History Ramp register. Short-
Page 20 of 70 Rev: 2.0
Date: September 28, 2011
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