STC5420 Datasheet, PDF (41/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
0= no change, 1 = T4 selected reference changed
Event6: T4 PLL status
0= no change, 1 = T0 PLL status changed
Event7: T4 timing generator’s event out
0= no event out, 1= any of T4 PLL event out is asserted or not cleared at the register of
PLL_Event_Out
Interrupts are cleared by writing “1” to the bit positions
Default value: 0
Interrupt_Event_Mask, 0x1B (R/W)
Address
0x1B
Bit7
Event 7
Bit6
Event 6
Bit5
Event 5
Bit4
Event 4
Bit3
Event 3
Bit2
Event 2
Bit1
Event 1
Bit0
Event 0
Selects which of events will assert the pin EVENT_INTR to active mode (See register Interrupt_Config).
0 = mask out, 1 = enable
Default value: 0
Interrupt_Config, 0x1C (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
0x1C
Not used
Active signal level
Sets the signal level in active mode.
0 = active low. 1 = active high
Idle mode
Specify the state of pin EVENT_INTR when no interrupt event occurs.
0 = tri-state. 1 = logic inactive
Default value: 0
Hard_Wired_Switch_Pre_Selection, 0x1D (R/W)
Bit2
Bit1
Bit0
Idle mode
Active sig-
nal level
Address
0x1D
Bit7
Bit6
Bit5
Bit4
Pre-selected reference number 2
Bit3
Bit2
Bit1
Bit0
Pre-selected reference number 1
Pre select reference number 1 and reference number 2 in hard-wired manual reference selection mode. This
mode is controlled by pin SRCSW. When pin SRCSW is LOW, reference number 1 is pre-selected. When pin
SRCSW is HIGH, reference number 2 is pre-selected. It only can be configured when bit7 of Control_Mode
register is set to 1 (See register Control_Mode).
Page 41 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011