STC5420 Datasheet, PDF (33/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
CS
WR
RD
A0-A6
AD0-AD7
RDY
t_WRBs
t_WRB
t_WRB1
t_WRBh
t_As
t_RDYd1
t_Ah
Address
t_Ds
t_Dh
Data
t_RDYd2
t_RDY
t_RDYh
t_RDYd3
Figure 14: Intel Bus Write Timing
Table 11: Intel Bus Write Timing
Symbol
t_WRBs
t_WRB
t_WRBh
t_WRB1
t_As
t_Ah
t_Ds
t_Dh
t_RDYd1
t_RDYd2
t_RDY
t_RDYh
t_RDYd3
Description
Write setup time
Write low time
Write hold time
Time between consecutive writes
Address setup
Address hold
Data setup time before WR high
Data hold time after WR high
CS low to RDY high delay
WR low to RDY low
RDY low time
WR hold after RDY high
RDY high-z delay after CS high
Min
Max
Unit
0
ns
40
ns
0
ns
50
ns
10
ns
0
ns
10
ns
10
ns
13
ns
40
ns
50
ns
0
ns
10
ns
Page 33 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011