STC5420 Datasheet, PDF (34/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
Multiplex Bus Mode
In multiplex bus mode, the device can interface with microprocessors which share the address and data on the
same bus signals. The ALE, CS, WR, RD, AD(0-7), and RDY pins are used. Timing is as follows in Figure 15
and Figure 16
Multiplex Bus Timing
t_ALE
t_ALEd
ALE
t_ADs
t_ADh
t_CSs
CS
WR
t_CSd
t_RDB
t_CSh
RD
AD0-AD7
t_Dd1
Address
t_Dh2
Data
RDY
t_RDYd1
t_RDYd2
t_RDY
t_RDYh
t_RDYd3
Figure 15: Multiplex Bus Read Timing
Table 12: Multiplex Bus Read Timing
Symbol
t_ALE
t_ALEd
t_ADs
t_ADh
t_CSs
t_RDB
t_CSh
t_CSd
t_Dd1
t_Dh2
t_RDYd1
t_RDYd2
t_RDY
t_RDYh
t_RDYd3
Description
ALE high time
ALE falling edge to RD low
Address setup time
Address hold time
Read setup time
Read time
CS hold time
CS delay for multiple read/writes
Data valid delay from RD low
Data high-z from RD high
CS low to RDY active
RD low to RDY low
RDY low time
RD hold after RDY high
RDY high-z delay after CS high
Min
Max
Unit
10
ns
0
ns
10
ns
10
ns
0
ns
40
ns
0
ns
50
ns
50
ns
10
ns
13
ns
40
ns
50
ns
0
ns
10
ns
Page 34 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011