STC5420 Datasheet, PDF (56/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
Register
Frame_Mux
(Bit9~Bit8)
X
X
0
1
2
3
X
Register
CLK7_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
CLK7 Synthesizer Select
Put CLK7 in tri-state mode
Synthesizer G₄ (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK7 tie to ground
Synthesizer G_T4 (T4)
Default value: 0
CLK8_Sel, 0x58 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x58
Not used
CLK8 Synthesizer Select
Selects the clock output CLK8 derived from synthesizer G₈ (T0), synthesizer F or synthesizer G_T4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit11~bit10 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or
Frame2K. Signal level of CLK8 is LVCMOS.
Register
Frame_Mux
(Bit11~Bit10)
X
X
0
1
2
3
X
Register
CLK8_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
Default value: 0
Frame8K_Sel, 0x59 (R/W)
Frame2K_Sel, 0x5A (R/W)
CLK8 Synthesizer Select
Put CLK8 in tri-state mode
Synthesizer G₄ (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK8 tie to ground
Synthesizer G_T4 (T4)
Address
Bit7
0x59
0x5A
Bit6
Invert
Invert
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Duty Cycle Select for Frame8K or put CLK8K into tri-state
Duty Cycle Select for Frame2K or put CLK2K into tri-state
Selects duty cycle of the Frame8K and Frame2K generated from synthesizer F and determine frame edge is
rising or falling. Set 0 Bit5~0 to put CLK8K/CLK2K into tri-state or put Frame8K/Frame2K of synthesizer F to
ground.
Page 56 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011