STC5420 Datasheet, PDF (18/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

tion as in master/slave configuration. In order to meet
same synchronization requirement, each unit should
use same parameter setup including loop bandwidth.
Multiple-master configuration demands a high quality
external oscillator to obtain a precise frame phase
alignment.
Control Interfaces
The STC5420’s controls interfaces are composed of
hardwire control pins and the bus interface. They
provide application access to the STC5420ís internal
control and status registers. This bus interface may
be configured among four type of micro-controller
interfaces, three of them are in parallel (Intel, Motor-
ola, Multiplexed) and one in serial (SPI). The selec-
tion of the bus interface is pin-controlled.
Field Upgradability
The STC5420 supports Field Upgradability which
allows the user to load size of 7600 byte firmware
configuration data (provided as per request) via bus
interface. It provides the user a flexible field solution
for different applications.
Advantage and Performance
The kernel of each timing generator is a DSP-based
PLL. In STC5420, all internal modules are either digi-
tal or numerical, including the phase detectors, filters,
and clock synthesizers. The revolutionary pure-digital
design makes the timing generator become an accu-
rate and reliable deterministic system. This modern
technology removes any external component except
the external oscillator. It provides excellent perfor-
mance and reliability to STC5420. A well-chosen
oscillator will make STC5420 meet all the synchroni-
zation requirements. Short-term stability associated
with the desired loop bandwidth is a more important
factor than aging projection and thermal response
when select an appropriate oscillator.
STC5420
Synchronous Clock for SETS
Data sheet
Functional Specification
Page 18 of 70 Rev: 2.0
Date: September 28, 2011
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice