STC5420 Datasheet, PDF (4/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
Table of Figures
Figure 1: Functional Block Diagram................................................................................................................... 1
Figure 2: Activity Monitor ................................................................................................................................. 22
Figure 3: Reference Qualification Scheme ...................................................................................................... 23
Figure 4: Automatic Reference Elector States................................................................................................. 24
Figure 5: Output Clocks CLK1 and CLK2 ........................................................................................................ 25
Figure 6: Output Clocks CLK3~CLK8.............................................................................................................. 25
Figure 7: Output Clocks CLK8K and CLK2K ................................................................................................... 26
Figure 8: SPI Bus, Read access (Pin CLKE = Low) ........................................................................................ 28
Figure 9: SPI Bus Timing, Read access (Pin CLKE = High) ........................................................................... 29
Figure 10: SPI Bus Timing, Write access ........................................................................................................ 29
Figure 11: Motorola Bus Read Timing ............................................................................................................ 30
Figure 12: Motorola Bus Write timing ............................................................................................................. 31
Figure 13: Intel Bus Read Timing ................................................................................................................... 32
Figure 14: Intel Bus Write Timing ................................................................................................................... 33
Figure 15: Multiplex Bus Read Timing............................................................................................................ 34
Figure 16: Multiplex Bus Write Timing ............................................................................................................ 35
Figure 17: Noise Transfer Functions .............................................................................................................. 62
Figure 18: Power and Ground ........................................................................................................................ 65
Page 4 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011