STC5420 Datasheet, PDF (54/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Register
Frame_Mux
(Bit1~Bit0)
1
2
3
X
Register
CLK3_Sel
(Bit1~Bit0)
2
2
2
3
STC5420
Synchronous Clock for SETS
Data sheet
CLK3 Synthesizer Select
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK3 tie to ground
Synthesizer G_T4 (T4)
Default value: 0
CLK4_Sel, 0x54 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x54
Not used
CLK4 Synthesizer Select
Selects the clock output CLK4 derived from synthesizer G₄ (T0), synthesizer F or synthesizer G_T4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit3~bit2 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or Frame2K.
Signal level of CLK4 is LVCMOS.
Register
Frame_Mux
(Bit3~Bit2)
X
X
0
1
2
3
X
Default value: 0
CLK5_Sel, 0x55 (R/W)
Register
CLK4_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
CLK4 Synthesizer Select
Put CLK4 in tri-state mode
Synthesizer G₄ (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK4 tie to ground
Synthesizer G_T4 (T4)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x55
Not used
CLK5 Synthesizer Select
Selects the clock output CLK5 derived from synthesizer G₅ (T0), synthesizer F or synthesizer G_T4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit5~bit4 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or Frame2K.
Signal level of CLK5 is LVCMOS.
Register
Frame_Mux
(Bit5~Bit4)
X
Register
CLK5_Sel
(Bit1~Bit0)
0
CLK5 Synthesizer Select
Put CLK5 in tri-state mode
Page 54 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011