STC5420 Datasheet, PDF(24/70 Page) Connor-Winfield Corporation

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STC5420 Datasheet, PDF (24/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

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STC5420

Synchronous Clock for SETS

Data sheet

ence will not be pre-empted by any new candidate

until it is disqualified.

If there is no candidate reference available, freerun or

holdover will be recommended by the automatic ref-

erence elector depending on the holdover history

availability.

Figure 4 shows the operation states for automatic ref-

erence elector.

Hard-wired Manual Reference Selection

Besides the manuaFl urenfecretinocneasleSlepcteiocnifimcoadteio, nthe

STC5420 provides a special mode to switch between

two pre-selected reference directly from a dedicated

pin SRCSW. The two pre-selected references are

configured at the register Hard Wired Switch Pre

Selection. It can make the device enter the freerun or

holdover by writing to the register Hard Wired Switch

Pre Selection. In this mode, the pin SRCSW oper-

ates as a simple switch by setting high or low. Hard-

wired Manual Reference Selection is for T0 only.

Candidate

Reference

Available

Elect

Candidate

Reference

Candidate

Reference

Available

Elect

Holdover

No Candidate

Reference

Available and

HO is Available

No Candidate

Reference

Available and

HO not Available

Elect

Freerun

Clock Outputs Details

The STC5420 generates 2 synchronized differential

(LVPECL or LVDS) clock outputs: CLK1 and CLK2; 6

LVCMOS clock outputs: CLK3~CLK8; frame pulse

clock outputs CLK8K and CLK2K. Figure 5, Figure 6,

and Figure 7 respectively shows the clock output sec-

tion for CLK1/CLK2, CLK8K/CLK2K, and

CLK3~CLK8. Each output has individual clock output

section consist of a synthesizer and a clock genera-

tor. Clock generator of CLK1 or CLK2 has a LVPECL/

LVDS driver to produce differential output. Each gen-

erator of CLK3~CLK8 includes two muxes and a LVC-

MOS signal driver. Generator of frame output CLK8K

and CLK2K consist of a LVCMOS driver.

Figure 4: Automatic Reference Elector States

Automatic Reference Selection

The T0 and T4 timing generators may be individually

operated automatic reference input selection mode.

The mode is selected via the Control Mode registers.

In automatic reference selection mode, the selected

reference is the same reference elected by the auto-

matic reference elector. The automatically selected

reference for each PLL may be read from the Auto

Elect Ref registers.

Manual Reference Selection Mode

In manual reference selection mode, the user may

select the reference manually. This mode is selected

via the Control Mode registers. The reference is

selected by writing to the Manual Select Ref regis-

ters. The user may also has the device enter freerun

or holdover manually by writing to the Manual Select

Ref registers. Besides, T4 may select T0âs output as

the selected reference.

Clock Synthesizers

The STC5420 has 10 clock synthesizers, which of 9

is disciplined by the timing generator T0: synthesizer

G1~G8 and one frame pulse clock synthesizer F; T4

disciplines a clock synthesizer GT4. Clock synthesiz-

ers G1~G8 produce frequencies from 1MHz to

156.25MHz, in 1kHz steps. Phase skew of these syn-

thesizers are all programmable individually up and

down 50ns at the register Synth Index Select and

Synth Skew Adj. CLK1 and CLK2 are derived from

synthesizer G1 and G2. CLK3 ~ CLK8 can be derived

from synthesizer G3~G8, also can be derived from

synthesizer F or from synthesizer GT4 respectively.

Synthesizer F produces frame pulse clock Frame8K,

Frame2K, and a proprietary composite signal. Syn-

thesizer F has two independent duty cycle controller

for Frame8K and Frame2K which can program pulse

width at the register Frame8K Sel and Frame2K Sel.

Proprietary composite signal is a 3.3V LVCMOS data

signal carries 8kHz clock, 2kHz frame, and the

selected reference information.

Page 24 of 70 Rev: 2.0

Date: September 28, 2011

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