STC5420 Datasheet, PDF (22/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420
Synchronous Clock for SETS
Data sheet
Reference Inputs Details
The STC5420 accepts 12 external reference inputs.
The reference inputs may be selected to accept either
the auto-detect acceptable reference frequency which
can be automatically detected by STC5420 or manu-
ally acceptable reference frequency. Reference
inputs REF11 and REF12 are LVPECL/LVDS and the
remaining ten are LVCMOS. Signal polarity of REF11
and REF12 is reversible at the register Diff Ref
Polarity. All 12 reference inputs are monitored contin-
uously for frequency, activity and quality. Each timing
generator may select any of the reference inputs
when the device is in external timing mode. T4 may
accept T0’s output as its input via internal feedback
path.
Acceptable Frequency and Frequency Offset
Detection
The STC5420 can automatically detect the frequency
of the reference input when the user enable the auto-
detection function at the register Ref Index Selector
and Ref Acceptable Freq. The acceptable auto-
detect frequencies are: 8kHz, 64kHz, 1.544MHz,
2.048MHz, 19.44MHz, 38.88MHz, 77.76MHz,
6.48MHz, 8.192MHz, 16.384MHz, 25MHz, 50MHz or
125MHz. These frequencies can be automatic
detected continuously in the detector. Any carrier fre-
quency change will be detected within 1ms. Each
input is also monitored for frequency offset between
input and the internal freerun clock. The frequency
offset is a key factor to determine qualification of the
reference inputs. See register Ref Index Selector
and Ref Info.
STC5420 provides another option which allows the
user to select the manually acceptable reference fre-
quency for all the reference inputs, at the integer mul-
tiple of 8kHz (Nx8kHz, N is integer from 1 to 32767).
Hence the manually acceptable reference frequency
range is integer multiple of 8kHz from 8kHz to
262.136MHz. When a manually acceptable reference
frequency is used, the user need to access the regis-
ter Ref Acceptable Freq to set the integer N for the
reference input which is selected at the register Ref
Index Selector. Each input is monitored for fre-
quency offset between input and the internal freerun
clock. The frequency offset is shown in the register
Ref Info when associate reference index is selected
at the register Ref Index Selector.
Activity Monitoring
Activity monitoring is^Fa^ulsⁿo^ca^tc^ioonⁿt^ain^lu^Sou^ps^ep^cro^ifcⁱe^cs^as^tiw^ohⁿich
is used to identify if the reference input is in normal. It
is accomplished with a leaky bucket accumulation
algorithm, as shown in Figure 2. The “leaky bucket”
accumulator has a fill observation window that may
be set from 1 to 16ms, where any hit of signal abnor-
mality (or multiple hits) during the window increments
the bucket count by one. The leak observation win-
dow is 1 to 16 times the fill observation window. The
leaky bucket accumulator decrements by one for
each leak observation window that passes with no
signal abnormality. Both windows operate in a con-
secutive, non-overlapping manner. The bucket accu-
mulator has alarm assert and alarm de-assert
thresholds that can each be programmed from 1 to
64.
Fill Observa-
tion Window,
1ms ~ 16ms
Frequency
Ref
Detector
Pulse
Monitor
Leaky
Bucket
Accumulator
Alarm Assert
Alarm De-Assert
Leak Observation
Window, 1~16 x Fill
Observation Window
Figure 2: Activity Monitor
Applications can write to the following registers to
configure the activity monitor: Fill Obs Window,
Leak Obs Window, Bucket Size, Assert Threshold,
and De Assert Threshold.
Setting the bucket size to 0 will bypass the leak
bucket accumulator and assert or de-assert the activ-
ity alarm based on results of frequency detector and
pulse monitor only. A non-zero bucket size must be
greater than or equal to the alarm assert threshold
value. The alarm assert threshold value must be
greater than the alarm de-assert threshold value and
less than or equal to the bucket size value. Attempted
writes of invalid values will be ignored. Therefore,
user must carefully plan an appropriate sequence of
writes when re-configure the activity monitor. See
register Bucket Size, Assert Threshold and De
Assert Threshold for details.
Page 22 of 70 Rev: 2.0
Date: September 28, 2011
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