STC5420 Datasheet, PDF (65/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Application Notes
STC5420
Synchronous Clock for SETS
Data sheet
This section describes typical application use of the STC5420 device. The General section applies to all appli-
cation variations.
General
Power and Ground
Well-planned noise-minimizing power and ground are essential to achieving the best performance of the
device. The device requires 3.3V digital power and analog power input.
It is desirable to provide individual 0.1uF bypass capacitors, located close to the chip, for each of the power
input leads, subject to board space and layout constraints.
Ground should be provided by as continuous a ground plane as possible. A separated analog ground plane is
recommended.
Note: Un-used reference inputs must be grounded.
3.3V digital
power
inputs
VCC
STC5420
MCLK
OCXO/
TCXO
3.3V analog
power
inputs
AVCC
GND
AGND
Digital ground
Analog ground
Figure 18: Power and Ground
Master Oscillator
An external 3.3V LVCMOS level clock (generally derived from TCXO or OCXO) is supplied at pin MCLK as
master clock. TCXO or OCXO should be carefully chosen as required by application. It is recommended that
the oscillator is placed close to the STC5420. Frequency of the master oscillator has four options, see descrip-
tion of the register MCLK Freq Reset for details.
Page 65 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011