STC5420 Datasheet, PDF (6/70 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5420 Pin Description
STC5420
Synchronous Clock for SETS
Data sheet
All I/O is LVCMOS, except for CLK1 and CLK2 are LVPECL/LVDS. REF11 and REF12 are LVPECL/LVDS.
Table 1: Pin Description
Pin Name
AVCC
AGND
VCC
GND
TRST
TCK
TMS
TDI
TDO
RST
MCLK
EVENT_INTR
MC/SL
EX_SYNC
REF1
REF2
REF3
REF4
REF5
REF6
REF7
REF8
REF9
REF10
REF11_P
REF11_N
REF12_P
Pin #
6,19,
5, 20
12, 13,
16, 33,
39, 50,
61, 85,
86, 91
1, 11, 14,
15, 32,
38, 49,
62, 84,
87, 92
2
9
7
23
21
74
10
8
99
45
46
47
48
51
52
53
54
55
56
57
40
41
42
I/O
3.3V analog power input
Analog ground
3.3V digital power input
Description
Digital ground
I JTAG boundary scan reset, active low
I JTAG boundary scan clock
I JTAG boundary scan mode selection
I JTAG boundary scan data input
O JTAG boundary scan data output
I Active low to reset the chip
I Master clock input (TCXO or OCXO)
O Event interrupt
I Select master or slave mode for T0
I Frame Sync signal
I Reference input 1
I Reference input 2
I Reference input 3
I Reference input 4
I Reference input 5
I Reference input 6
I Reference input 7
I Reference input 8
I Reference input 9
I Reference input 10
I Differential reference input 11 positive(LVPECL/LVDS)
I Differential reference input 11 negative(LVPECL/LVDS)
I Differential reference input 12 positive(LVPECL/LVDS)
Page 6 of 70
Rev:2.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 28, 2011