EP3SL110F1152C2N Datasheet, PDF (81/341 Pages) Altera Corporation – Stratix III Device Handbook,

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–71
Table 1–53 lists the EP3SL70 column pins output timing parameters for single-ended
I/O standards.
Table 1–53. EP3SL70 Column Pins Output Timing Parameters (Part 1 of 7)
I/O
Standard
Clock
3.3-V
LVTTL
3.3-V
LVCMOS
3.0-V
LVTTL
GCLK t_co
4mA _GCLK
PLL ^tco
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
GCLK t_co
16mA _GCLK
PLL ^tco
GCLK t_co
4mA _GCLK
PLL ^tco
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
GCLK t_co
16mA _GCLK
PLL ^tco
GCLK t_co
4mA _GCLK
PLL ^tco
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
GCLK t_co
16mA _GCLK
PLL ^tco
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
3.187
3.187 4.411 4.765 5.226 5.105 5.313 4.765 5.226 5.105 5.313 ns
3.514
3.514 4.895 5.293 5.823 5.680 5.963 5.293 5.823 5.680 5.963 ns
3.120
3.120 4.302 4.654 5.113 4.992 5.200 4.654 5.113 4.992 5.200 ns
3.447
3.447 4.786 5.182 5.710 5.567 5.850 5.182 5.710 5.567 5.850 ns
3.034
3.034 4.198 4.556 5.021 4.900 5.108 4.556 5.021 4.900 5.108 ns
3.361
3.361 4.682 5.083 5.618 5.475 5.760 5.083 5.618 5.475 5.760 ns
3.028
3.028 4.182 4.528 4.980 4.859 5.067 4.528 4.980 4.859 5.067 ns
3.354
3.354 4.665 5.055 5.577 5.434 5.718 5.055 5.577 5.434 5.718 ns
3.193
3.193 4.415 4.770 5.233 5.112 5.320 4.770 5.233 5.112 5.320 ns
3.520
3.520 4.899 5.298 5.830 5.687 5.971 5.298 5.830 5.687 5.971 ns
3.038
3.038 4.209 4.573 5.032 4.911 5.119 4.573 5.032 4.911 5.119 ns
3.365
3.365 4.692 5.100 5.629 5.486 5.770 5.100 5.629 5.486 5.770 ns
3.045
3.045 4.203 4.552 5.006 4.885 5.093 4.552 5.006 4.885 5.093 ns
3.372
3.372 4.686 5.079 5.603 5.460 5.746 5.079 5.603 5.460 5.746 ns
3.029
3.029 4.180 4.527 4.977 4.856 5.064 4.527 4.977 4.856 5.064 ns
3.356
3.356 4.664 5.054 5.574 5.431 5.717 5.054 5.574 5.431 5.717 ns
3.150
3.150 4.378 4.733 5.193 5.072 5.280 4.733 5.193 5.072 5.280 ns
3.478
3.478 4.862 5.261 5.790 5.647 5.954 5.261 5.790 5.647 5.954 ns
3.043
3.043 4.250 4.602 5.056 4.936 5.142 4.602 5.056 4.936 5.142 ns
3.367
3.367 4.732 5.127 5.652 5.510 5.837 5.127 5.652 5.510 5.837 ns
3.005
3.005 4.184 4.530 4.982 4.862 5.068 4.530 4.982 4.862 5.068 ns
3.331
3.331 4.669 5.058 5.578 5.436 5.773 5.058 5.578 5.436 5.773 ns
2.986
2.986 4.156 4.503 4.953 4.832 5.040 4.503 4.953 4.832 5.040 ns
3.313
3.313 4.640 5.030 5.550 5.407 5.750 5.030 5.550 5.407 5.750 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2