EP3SL110F1152C2N Datasheet, PDF (139/341 Pages) Altera Corporation – Stratix III Device Handbook,

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–129
Table 1–73. EP3SL150 Column Pins Output Timing Parameters (Part 6 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
SSTL-15
CLASS II
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
16mA _GCLK
PLL ^tco
3.251
3.674
3.254
3.677
3.268
3.670
3.271
3.673
4.617 4.983 5.486 5.334 5.669 4.983 5.486 5.334 5.669 ns
5.204 5.648 6.202 6.022 6.404 5.648 6.202 6.022 6.404 ns
4.624 4.992 5.497 5.345 5.680 4.992 5.497 5.345 5.680 ns
5.211 5.657 6.213 6.033 6.415 5.657 6.213 6.033 6.415 ns
GCLK t_co 3.261
4mA
GCLK
PLL ^tco
3.684
3.278
3.680
4.619 4.983 5.484 5.332 5.667 4.983 5.484 5.332 5.667 ns
5.206 5.648 6.200 6.020 6.402 5.648 6.200 6.020 6.402 ns
GCLK t_co 3.254
6mA
GCLK
PLL ^tco
3.677
3.271
3.673
4.617 4.982 5.483 5.331 5.666 4.982 5.483 5.331 5.666 ns
5.204 5.647 6.199 6.019 6.401 5.647 6.199 6.019 6.401 ns
1.8-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
3.246
3.669
3.263
3.665
4.609 4.974 5.476 5.324 5.659 4.974 5.476 5.324 5.659 ns
5.196 5.639 6.192 6.012 6.394 5.639 6.192 6.012 6.394 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.249
3.672
3.266
3.668
4.612 4.978 5.480 5.328 5.663 4.978 5.480 5.328 5.663 ns
5.199 5.643 6.196 6.016 6.398 5.643 6.196 6.016 6.398 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.246
3.669
3.263
3.665
4.615 4.981 5.484 5.332 5.667 4.981 5.484 5.332 5.667 ns
5.202 5.646 6.200 6.020 6.402 5.646 6.200 6.020 6.402 ns
1.8-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.254
3.677
3.271
3.673
4.614 4.979 5.480 5.328 5.663 4.979 5.480 5.328 5.663 ns
5.201 5.644 6.196 6.016 6.398 5.644 6.196 6.016 6.398 ns
GCLK t_co 3.266
4mA
GCLK
PLL ^tco
3.689
3.283
3.685
4.627 4.993 5.495 5.343 5.678 4.993 5.495 5.343 5.678 ns
5.214 5.658 6.211 6.031 6.413 5.658 6.211 6.031 6.413 ns
GCLK t_co 3.262
6mA
GCLK
PLL ^tco
3.685
3.279
3.681
4.628 4.995 5.498 5.346 5.681 4.995 5.498 5.346 5.681 ns
5.215 5.660 6.214 6.034 6.416 5.660 6.214 6.034 6.416 ns
1.5-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
3.258
3.681
3.275
3.677
4.624 4.990 5.493 5.341 5.676 4.990 5.493 5.341 5.676 ns
5.211 5.655 6.209 6.029 6.411 5.655 6.209 6.029 6.411 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.251
3.674
3.268
3.670
4.617 4.983 5.486 5.334 5.669 4.983 5.486 5.334 5.669 ns
5.204 5.648 6.202 6.022 6.404 5.648 6.202 6.022 6.404 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.252
3.675
3.269
3.671
4.624 4.991 5.496 5.344 5.679 4.991 5.496 5.344 5.679 ns
5.211 5.656 6.212 6.032 6.414 5.656 6.212 6.032 6.414 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2