EP3SL110F1152C2N Datasheet, PDF (120/341 Pages) Altera Corporation – Stratix III Device Handbook,

1–110
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–65. EP3SL110 Column Pins Input Timing Parameters (Part 2 of 2)
I/O Standard Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su
DIFFERENTIAL ^GCLK
1.8-V HSTL
t_h
CLASS II
GCLK ^tsu
PLL _th
DIFFERENTIAL
1.5-V SSTL
GCLK
t_su
t_h
CLASS I
GCLK ^tsu
PLL _th
t_su
DIFFERENTIAL ^GCLK
1.5-V SSTL
t_h
CLASS II
GCLK ^tsu
PLL _th
t_su
DIFFERENTIAL ^GCLK
1.8-V SSTL
t_h
CLASS I
GCLK ^tsu
PLL _th
DIFFERENTIAL
1.8-V SSTL
GCLK
t_su
t_h
CLASS II
GCLK ^tsu
PLL _th
t_su
DIFFERENTIAL ^GCLK
2.5-V SSTL
t_h
CLASS I
GCLK ^tsu
PLL _th
t_su
DIFFERENTIAL ^GCLK
2.5-V SSTL
t_h
CLASS II
GCLK ^tsu
PLL _th
-0.814
0.933
1.131
-0.878
-0.802
0.921
1.143
-0.890
-0.802
0.921
1.143
-0.890
-0.814
0.933
1.131
-0.878
-0.814
0.933
1.131
-0.878
-0.821
0.940
1.124
-0.871
-0.821
0.940
1.124
-0.871
-0.852
0.990
1.155
-0.881
-0.841
0.979
1.166
-0.892
-0.841
0.979
1.166
-0.892
-0.852
0.990
1.155
-0.881
-0.852
0.990
1.155
-0.881
-0.858
0.996
1.149
-0.875
-0.858
0.996
1.149
-0.875
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 ns
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040 ns
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062 ns
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 ns
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 ns
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022 ns
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080 ns
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 ns
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 ns
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022 ns
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080 ns
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 ns
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 ns
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040 ns
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062 ns
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 ns
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 ns
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040 ns
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062 ns
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 ns
-1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815 ns
1.449 1.576 1.715 1.648 2.003 1.583 1.717 1.653 2.041 ns
1.777 2.004 2.210 2.102 2.014 2.023 2.238 2.124 2.066 ns
-1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575 ns
-1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815 ns
1.449 1.576 1.715 1.648 2.003 1.583 1.717 1.653 2.041 ns
1.777 2.004 2.210 2.102 2.014 2.023 2.238 2.124 2.066 ns
-1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575 ns
Table 1–66 lists the EP3SL110 parameters for differential I/O standards.
Table 1–66. EP3SL110 Row Pins Input Timing Parameters (Part 1 of 3)
I/O Standard
LVDS
Clock
GCLK
GCLK
PLL
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su -0.919
t_h 1.043
t_su 0.959
t_h -0.698
-0.950
1.092
0.987
-0.708
-1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442 ns
1.245 1.237 1.395 1.339 1.672 1.207 1.358 1.303 1.711 ns
1.949 2.324 2.527 2.403 2.334 2.384 2.597 2.470 2.387 ns
-1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation