EP3SL110F1152C2N Datasheet, PDF (23/341 Pages) Altera Corporation – Stratix III Device Handbook,

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
1–13
Switching Characteristics
This section provides performance characteristics of Stratix III core and periphery
blocks for commercial grade devices.
These characteristics can be designated as Preliminary and Final and each
designation is defined below.
Preliminary—Preliminary characteristics are created using simulation results, process
data, and other known parameters.
Final—Final numbers are based on actual silicon characterization and testing. These
numbers reflect the actual performance of the device under worst-case silicon process,
voltage, and junction temperature conditions. The upper-right hand corner of a table
shows the designation as Preliminary or Final.
Core Performance Specifications
These sections describe the Clock Tree, PLL, digital signal processing (DSP),
TriMatrix, and Configuration and JTAG specifications.
Clock Tree Specifications
Table 1–19 lists the clock tree performance specifications for the logic array, DSP
blocks, and TriMatrix Memory blocks for Stratix III devices.
Table 1–19. Clock Tree Performance for Stratix III Devices
Device
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SE260
EP3SL340
EP3SE50
EP3SE80
EP3SE110
C2
C3, I3
V_CCL = 1.1 V
730
730
730
730
730
730
730
730
730
730
V_CCL = 1.1 V
700
700
700
700
700
700
700
700
700
700
C4, I4
V_CCL = 1.1 V
450
450
450
450
450
450
450
450
450
450
C4L, I4L
Unit
V_CCL = 1.1 V V_CCL = 0.9 V
450
375
MHz
450
375
MHz
450
375
MHz
450
375
MHz
450
375
MHz
450
375
MHz
450
375
MHz
450
375
MHz
450
375
MHz
450
375
MHz
PLL Specifications
Table 1–20 lists the Stratix III PLL specifications when operating in both the
commercial junction temperature range (0 to 85° C) and the industrial junction
temperature range (-40 to 100° C), except for EP3SL340, EP3SE260, and EP3SL200
devices in the I4L ordering code, where the industrial junction temperature range is
from 0° C to 100° C, regardless of supply voltage. Refer to the figure in “PLL
Specifications” in “Glossary” on page 1–326 for the PLL block diagram.
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2