EP3SL110F1152C2N Datasheet, PDF (329/341 Pages) Altera Corporation – Stratix III Device Handbook,

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–319
Table 1–176 and Table 1–177 list the periphery clock timing parameters for EP3SL340
devices.
Table 1–176. EP3SL340 Column Pin Periphery Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
C2
C3
C4
C4L
Industrial
1.778
1.778
0.086
0.086
Commercial
1.760
1.760
0.061
0.061
V_CCL=
1.1 V
V_CCL=
1.1 V
2.687 2.847
2.687 2.847
-0.164 -0.161
-0.164 -0.161
V_CCL=
1.1 V
3.240
3.240
-0.140
-0.140
V_CCL=
1.1 V
3.099
3.099
-0.097
-0.097
V_CCL=
0.9 V
3.718
3.718
0.101
0.101
I3
I4
I4L
V_CCL=
1.1 V
2.847
2.847
-0.161
-0.161
V_CCL=
1.1 V
3.240
3.240
-0.140
-0.140
V_CCL=
1.1 V
3.099
3.099
-0.097
-0.097
V_CCL=
0.9 V
3.718
3.718
0.101
0.101
Units
ns
ns
ns
ns
Table 1–177. EP3SL340 Row Pin Periphery Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial Commercial
1.524
1.442
0.116
0.034
1.616
1.525
0.211
0.120
C2
V_CCL=
1.1 V
2.435
2.280
-0.039
-0.191
C3
V_CCL=
1.1 V
2.567
2.404
-0.116
-0.279
C4
V_CCL=
1.1 V
2.958
2.777
-0.055
-0.236
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.823 3.141
2.652 2.982
-0.030 -0.051
-0.201 -0.210
I3
V_CCL=
1.1 V
2.605
2.435
-0.040
-0.210
I4
V_CCL=
1.1 V
3.002
2.813
-0.006
-0.195
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.861 3.165
2.682 3.006
0.050 -0.098
-0.129 -0.257
Units
ns
ns
ns
ns
EP3SE50 Clock Timing Parameters
Table 1–178 and Table 1–179 list the global clock timing parameters for EP3SE50
devices.
Table 1–178. EP3SE50 Column Pin Global Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
C2
C3
C4
C4L
Industrial
1.786
1.786
0.023
0.083
Commercial
1.789
1.789
0.027
0.103
V_CCL=
1.1 V
V_CCL=
1.1 V
2.495 2.748
2.495 2.748
-0.204 -0.268
-0.068 -0.131
V_CCL=
1.1 V
3.111
3.111
-0.226
-0.226
V_CCL=
1.1 V
2.993
2.993
-0.180
-0.010
V_CCL=
0.9 V
3.489
3.489
0.025
0.025
I3
V_CCL=
1.1 V
2.748
2.748
-0.268
-0.131
I4
V_CCL=
1.1 V
3.105
3.105
0.249
0.249
I4L
V_CCL=
1.1 V
2.993
2.993
-0.180
-0.010
V_CCL=
0.9 V
3.489
3.489
0.025
0.025
Units
ns
ns
ns
ns
Table 1–179. EP3SE50 Row Pin Global Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial Commercial
1.739
1.657
0.044
-0.038
1.849
1.758
0.117
0.026
C2
C3
C4
V_CCL=
1.1 V
V_CCL=
1.1 V
V_CCL=
1.1 V
2.536 2.769 3.112
2.394 2.606 2.931
-0.143 -0.220 -0.183
-0.285 -0.383 -0.364
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
3.010 3.250
2.839 3.091
-0.135 -0.189
-0.306 -0.348
I3
V_CCL=
1.1 V
2.830
2.660
-0.171
-0.341
I4
V_CCL=
1.1 V
3.171
2.982
0.345
0.156
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
3.069 3.276
2.890 3.117
-0.088 -0.242
-0.267 -0.401
Units
ns
ns
ns
ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2